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SKarp6's avatar
SKarp6
Icon for New Contributor rankNew Contributor
6 years ago

AXI Translator from Platform Designer (QSYS) doesn't follow AXI4-Lite protocol spec.

Hello All, This might be a known problem. It looks like AXI Translator module has a bug. When you pick AXI4-Lite on master side AXI Translator expects that RID and BID signals will be set by a modul...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Best Regards,
Shyan Yew