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SKarp6's avatar
SKarp6
Icon for New Contributor rankNew Contributor
5 years ago

AXI Translator from Platform Designer (QSYS) doesn't follow AXI4-Lite protocol spec.

Hello All, This might be a known problem. It looks like AXI Translator module has a bug. When you pick AXI4-Lite on master side AXI Translator expects that RID and BID signals will be set by a modul...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Sorry that the case had been idling for quite sometimes. Do you able to solve the issue?

Is there any help still needed from your side?