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SKarp6's avatar
SKarp6
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6 years ago

AXI Translator from Platform Designer (QSYS) doesn't follow AXI4-Lite protocol spec.

Hello All, This might be a known problem. It looks like AXI Translator module has a bug. When you pick AXI4-Lite on master side AXI Translator expects that RID and BID signals will be set by a modul...
SKarp6's avatar
SKarp6
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6 years ago

Attached waveforms of AXI LW interface captured with Signaltap for two different cases when SW reads slave. For hanging case RID signal remains zero.