Honored Contributor
Honored ContributorThe fabric uses slave side arbitration so if you have multiple masters then as long as they don't access the same slave you can have multiple transfers occuring concurrently. This is because Avalon-MM isn't a bus, it's an interface standard built on top of a partially (or fully depending on your design) crossbar switch.
Don't bother using bursting for anything that doesn't require it. For example bursting into a FIFO doesn't make much sense since a FIFO doesn't require a burst to be fast. Use bursting for things that could use it like off-chip interfaces that require bursting to be efficient. For what you are doing it sounds like you could use a streaming and memory mapped hybrid approach. Use streaming for the FIFO connections since by their very nature, FIFOs *are* just a stream of data. On the other side of your custom block you would read/write the stream to memory. Take a look at the Qsys tutorial, you'll see something similar to what I'm talking about except instead of FIFOs the data stream are data pattern generators/checkers: http://www.altera.com/support/examples/design-entry-tools/qsys/exm-qsys-tut.html
