Honored ContributorHey,
my goal is to access ddr3 Memory from the outside of my Qsys system where the DDr3 Controller is implemented. Has anyone a Template for a Master interface to access the memory from outside the qsys system or is it better to design my own IP core with my VHDL code that i am able to connect everything in the qsys environment. thanks Rene
Honored ContributorI'd go for own core. I've used it for my DMA.
Honored ContributorWhat template you used for your own core? can u upload them or link them?
ReneHonored ContributorIn Qsys: Add new component and there will be templates menu. Although, I used signals from manual, no need for template.
Honored ContributorHey tanks for your quick reply,
i found the template and get a new component. is there any example vhdl/ verilog file for the usage of this component. I think about a small file that read/write data with this interface to a ddr3 ram. ReneHonored Contributoras always - read the documentation, all signals are clearly described and waveforms shown.
Honored Contributoryeah but maybe someone done it before and is ready to share it with me.
thanks Rene
