Forum Discussion

PElm's avatar
PElm
Icon for New Contributor rankNew Contributor
7 years ago

Automatic use of internal block RAMs

I'm translating code from Xilinx devices to Intel to see if we could switch to Altera FPGAs. Xilinx tools automatically translate VHDL memory operations to block-ram without need to use macros or co...
PElm's avatar
PElm
Icon for New Contributor rankNew Contributor
7 years ago

@Daixiwen​ @Tricky​

I changed to using signals instead and read/write in the same process.

It works fine and one memory is created. However this only works when I'm not initializing the memory content. Then everything becomes logic again.

I don't understand how Altera want me to write the initialization of the memory content in VHDL.