Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Asynchronous FIFO implementation (clock domain crossing)

Let's say I have a shift register (called system A) that is operating at a clock frequency of 3f. The output of system A is fed into another shift register, system B, that operates at a frequency of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You can directly connect the A output to the B input if 3f and f clocks are synchronous, namely if they have a fixed and well defined phase relationship.