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Honored Contributor
Honored ContributorAsynchronous FIFO implementation (clock domain crossing)
Let's say I have a shift register (called system A) that is operating at a clock frequency of 3f. The output of system A is fed into another shift register, system B, that operates at a frequency of ...
Altera_ForumHonored Contributor
Honored ContributorHi,
are the two clocks derived from a common source, e.g. by using one PLL with two different clock outputs? If so, you should be able to define a multicycle exception in your timing constraints, and let TimeQuest figure out whether that works or not. I have to admit I've never done that, though, but there are various articles about that specific problem, e.g. here: http://www.alterawiki.com/wiki/timing_constraints#multicycles (http://www.alterawiki.com/wiki/timing_constraints#multicycles), or in the TimeQuest Cookbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_timequest_cookbook.pdf). It's just a gut feeling, but even if you use a single PLL I'd rather use some phase shift between the two clocks, so that the launch and latch clock are well apart. If the two clocks come from different sources (e.g. a 25 MHz XO and a 75 MHz XO), the two clocks must be seen as asynchronous, and proper clock domain crossing synchronization is inevitable. I know that's not exactly your question, but the Altera MegaWizard offers asynchronous FIFOs (i.e. with separate clocks on either side), if you need synchronization. Best regards, GooGooCluster
