Async IO Constraints

With these timings your approach of CDC with 200 MHz should work. You would need 4 clocks before the data gets output from internal ram (5 if you register that output). It should be possible to meet the set-up requirement. The output delay from RAM to pin may be a bit too high, so you may have to crank that clock up a little.

But as there is no relation between the 100 MHz CPU clock and the 200 MHz FPGA clock you cannot define an SDC constraint for this. So you would have to verify the 'correctness by design and inspection'.

I would be pleased to find someone learn us how this can be expressed in SDC-constraints.