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Altera_Forum
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14 years ago

Async IO Constraints

Hello, I need some guidance in figuring out how to specify my IO constraints. I have a CPU mapping the FPGA as a memory device. The CPU provides these signals: address - CPU --> FPGA re...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I'd say there is no relation between those two clocks, unless they happen to be derived from the same oscillator.