Arria V GX: Couldn't place LVDS outputs.

Hello, everyone.

I'm trying to implement 12 bits LVDS outputs in Arria V GX using Quartus II 13.1.

In the implementation, the altlvds_tx has 12 chunnels and the deserialization factor is 8 (that is, the input is tx_in[95..0]).

Simlations seems to work as I design.

However, errors below occur when I/O Assignment Analysis or Fitter executes.

**************************************************************

Error(175001):Could not place PLL LVDS output.

(Submessage)

Error (180002): Can't place PLL LVDS output because the SERDES DPA is already driven by 2 clock and clock enable pairs (16 locations affected)

Info (175029): PLLLVDSOUTPUT_X0_Y21_N2

Info (175029): PLLLVDSOUTPUT_X0_Y22_N2

Info (175029): PLLLVDSOUTPUT_X0_Y23_N2

Info (175029): PLLLVDSOUTPUT_X0_Y24_N2

Info (175029): PLLLVDSOUTPUT_X0_Y63_N2

Info (175029): PLLLVDSOUTPUT_X0_Y64_N2

Info (175029): PLLLVDSOUTPUT_X0_Y65_N2

Info (175029): PLLLVDSOUTPUT_X0_Y66_N2

Info (175029): PLLLVDSOUTPUT_X81_Y80_N2

Info (175029): PLLLVDSOUTPUT_X81_Y81_N2

Info (175029): PLLLVDSOUTPUT_X81_Y82_N2

Info (175029): PLLLVDSOUTPUT_X81_Y83_N2

Info (175029): and 4 more locations not displayed

Error (180002): Can't place PLL LVDS output because the SERDES DPA is already driven by 2 clock and clock enable pairs (8 locations affected)

Info (175029): PLLLVDSOUTPUT_X81_Y5_N2

Info (175029): PLLLVDSOUTPUT_X81_Y6_N2

Info (175029): PLLLVDSOUTPUT_X81_Y7_N2

Info (175029): PLLLVDSOUTPUT_X81_Y8_N2

Info (175029): PLLLVDSOUTPUT_X169_Y21_N2

Info (175029): PLLLVDSOUTPUT_X169_Y22_N2

Info (175029): PLLLVDSOUTPUT_X169_Y23_N2

Info (175029): PLLLVDSOUTPUT_X169_Y24_N2

****************************************************************

How can I work around these errors?

I'd be happy if anyone give me some advice.