Arria V Formal verification problems

Hi everyone,

I want to do a formal verification of a project where i use a Arria V FPGA, and to do this i'm planning to use Encounter Conformal Software, that is a Cadence tool But i'm not having much success.

I'm trying to follow these step by step that i found:

http://quartushelp.altera.com/14.1/mergedprojects/eda/verification/conformal/eda_pro_lec_setup.htm

To do this verification, i need to generate 2 files for Encounter Tool: a verilog output file (.vo) and a verilog quartus mapping file (.vqm). I generated the .vo without any problems but when i try to generate the .vqm, i get the following error: "Quartus II does not support the generation of .vqm for this family"

Ps: In the link above, Altera says that Arria family is supported for this flow.

Did anyone else already have this problem?

Thanks,