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Altera_Forum
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15 years ago

Arria II GX PCIe TLP payload issue

I am using Arria II GX FPGA in my PCIe cards and PCIe Hard IP with Avalon Streaming interface. I am using Quartus 9.1 SP1. I have configured the PCIe core to have a maximum TLP payload of 256 bytes(I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

an update:

I signaltapped the tx_cred0 port and it looks like even after sending a 256 bytes TLP packet, the posted data credit seem to decrease by 128 bytes. The numbers that I am seeing with the posted data credit is initial x40 and after sending a 256 bytes TLP packet the credit goes to x38. Which means that the posted data credit has decreased by 128 bytes(x40-x38= 8, 8x16 = 128 bytes).

I was wrong about tx_st_ready, it seems to high while the posted data credit is zero.

Any thoughts about the issue?

Thanks,

Kumaran