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FPGAOLOG's avatar
FPGAOLOG
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Arria 10 DSP resulta=(ay+az)*ax, resultb=(by+bz)*bx possible?

Arria 10 DSP resulta=(ay+az)*ax, resultb=(by+bz)*bx possible?
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

You can also refer to section 3.2.2 pre-adder that stated it can configure in 2 independent 18 bits pre-adder. You may explore it from the " Pre-adder" tab in Native Fixed-Point DSP Intel Arria 10 FPGA IP.