Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi,
> Your VHDL code is *not* written in a style that maps well to hardware. For example, FPGA RAM comes in specific sizes. In general, the synthesis tool will not "optimize" your arrays of arrays for you, and map them efficiently into various RAMs. Its really up to you as the designer to understand how to use the dual-ported RAM in the FPGA, the sizes of the various blocks in the FPGA, and then write code to efficiently move data into and out of those RAMs. Yes, the compiler told me that. But i have to read out multiple values of these data tables simultaneously and asynchroneously in various different code locations (the contents are i.e. parameters for pedestal and threshold corrections of the analog values of the individual silicon sensor strips, and later also e.g. for FIR-filter-parameters etc..., and there are multiple stages of these corrections which use the same tables...), so i think that normal dual-ported RAM does not work here. Whenever possible, I of course use optimized RAMs as found in alteras design recommendations. > ask further questions I will do that, thanks :-) Best regards :-)