Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- Thanks for the offer; but i workarounded the problem for now: I put the RAMs directly into bla instead of blubb instead of instantiating it, and implemented a protocol to read and write from and to the RAM in blubb... (maybe i will have a closer look to the problem again later, but now i can't invest more time in that :-) ). --- Quote End --- Rather that try and "work-around" something, you should try to understand the language first. Understanding how to use VHDL will serve you well in the longer run. --- Quote Start --- If you are interested in what the electronics i am developing is for: Its the readout system (including analog-to-digital-conversion and first level data processing) of a silicon detector of a particle accelerator (very similar to that of the LHC at CERN). --- Quote End --- Cool. Are these various boards supposed to talk to each other? Your VHDL code is *not* written in a style that maps well to hardware. For example, FPGA RAM comes in specific sizes. In general, the synthesis tool will not "optimize" your arrays of arrays for you, and map them efficiently into various RAMs. Its really up to you as the designer to understand how to use the dual-ported RAM in the FPGA, the sizes of the various blocks in the FPGA, and then write code to efficiently move data into and out of those RAMs. If your VME bus has a main host computer, and the FPGA boards are configured to DMA data back and forth to that host computer, then you need to understand how bridges and DMA controllers work. The array of arrays you are "playing" with now might actually be a cascade of various protocols, eg., ADC samples the data and writes that data into a doubled-buffered dual-port RAM, when the RAM is filled, a DMA is initiated so that the data is transferred to the host, or to another FPGA board in the VME backplane. This system can easily be described in VHDL and simulated (as a system) in Modelsim. Once your simulation works, you can synthesis the multiple designs, and test them in hardware. You commented that you are new to VHDL. Don't be afraid to ask questions on this forum. Just make sure to ask intelligent questions, i.e., show you have tried to figure things out, and when someone gives you advice, take it, or if you could not understand the advice, ask further questions. Cheers, Dave