Array en VHDL

You want that I make like that :

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cdm is

--generic (

-- width : natural :=4);

port (

clk : in std_logic ;

rst : in std_logic ;

data: in std_logic ;

odata: out std_logic ;

CD : in std_logic_vector(15 downto 0) ;

isis :out integer range 0 to 3 ;

S :out std_logic_vector(3 downto 0 ));

end entity ;

architecture beh of cdm is

--type tab is array(3 downto 0)of std_logic_vector(15 downto 0);

signal i :integer range 0 to 3 ;

signal idata :std_logic ;

--signal itab :tab ;

begin

code :process(clk,rst)

begin

if(rst='1')then

i<="0000" ;

else

if(clk'event and clk='1')then

i<=i+1 ;

case i is

when 0 =>s(0)<=not(CD(15 downto 12) xor (data));

when 1 =>s(1)<=not(CD(11 downto 8) xor (data));

when 2 =>s(2)<=not(CD(7 downto 4) xor (data));

when 3 =>s(3)<=not(CD(3 downto 0) xor (data));

if i=3 then

idata<=data ;

end if ;

end case ;

end if ;

end if ;

end process ;

isis<=i;

odata<=idata ;

end architecture ;

?? ! Thank you in advance