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CNgu
New Contributor
New ContributorAre there any good debugging tools that can help us troubleshoot easily?
We currently using quartus ii web edition version 13sp1. We are trying to deploy a solution for our customer using Altera Cyclone 2 FPGA. However, we are running into a problem related to state tran...
JOHI
Contributor
ContributorIf your state machine has inputs, make sure you buffer (synchronise) these inputs with the clock. Otherwise, your logic network that defines transitions from one state to another could be in a transition and not in a stable state when your state variable is updated.
