--- Quote Start ---
To both you guys (and anyone else reading):
Okay, I'll give verilog a try. But seriously, don't you guys have one big "block diagram" for your FPGA designs? Sure, I write huge software applications that don't have a single visual "block diagram" (though often I do draw one). But at least I have many clearly distinguished "subsystems" that perform the same purpose.
--- Quote End ---
Yes we do - but its often documented in MS Visio and Word. Where I work we need logic that compiles for both Xilinx AND Altera devices. So altera or xilinx schemtics are out the window (even if we wanted to use them) as they are proprietary. There is Mentor's HDL designer, which you may really like - which works from a graphical POV but underneath works with HDL (VHDL or Verilog). But there are issues:
1. It imposes it's own directory structures
2. You have to keep all the graphical files along with the HDL in version control.
3. Its not cheap, and it's only a code visualisation tool.
There are some people out there who absolutly love it, afaik none of the members of our 30 strong firmware team use it any more, mostly for the above reasons.
--- Quote Start ---
But I think the main problem (for me) is the fundamental difference between hardware and software. In hardware everything in the circuit is happening all the time. The entire schematic is "executing" constantly (or at least on every clock edge). While in software, one statement at one place is executing at any given moment. Very different!
--- Quote End ---
Yes. Which is why HDL works like a schematic. As long as you follow the basic templates you can code from a single and gate all the way up to a massive 64bit CPU (How do you think CPUs are designed now?). The synthesisors will even try to convert all behavioural code, and do quite a good job.
--- Quote Start ---
I've got to assume that EVERY wire in HDL, no matter how trivial, must have a name. Otherwise it couldn't get from one place to another. While on a schematic, everything close-by or related is simply connected by a line (a wire) or a bus (a bundle of 8, 16, 32, 64 ordered wires).
This must create a massive overabundance of names!
--- Quote End ---
You can create busses in HDL. You just create arrays in Verilog. In VHDL you can create record types for more complex busses:
type my_bus_t is record
addr : std_logic_vector(13 downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
end record my_bus_t;
and then at the port level:
port (
my_input_bus : in my_bus_t;
....
And that encapsulates multiple busses within a single name (and you can still access individual elements).
And Im sure verilog has similar (well it has at least arrays)
--- Quote End ---
--- Quote Start ---
And so my question is this. Do you know any book or tutorials or information sources that approach verilog in this bottom-up manner?
--- Quote End ---
There are many tutorials online, and they should all teach you the language through the basic elements.
As VHDL person - I dont know any good Verilog books, but Im sure there are people here who can.
Honored Contributor
