Honored Contributor
Honored ContributorI know it's not what you're asking, but why? Besides being an extremely inefficient way to do design, I've almost never seen someone get better results than letting synthesis figure out the best implementation. This is especially true for Stratix II/III/IV architectures with the Adaptive LUT, where it's not just how something gets synthesized but what inputs can be shared with other LUTs to get the best performance/area out of the architecture.
(The time to do this is when you've let the synthesizer do generic code and found it to be wrong, and are trying to tweak a small section. My comment above is for the designer trying to do lots of logic like this because they had to do it in Xilinx.) The first thing I would look at is the designing with low-level primitives app note: http://www.altera.com/literature/ug/ug_low_level.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=altera%20primitives I've used the LCELL method before, and have just done it in a schematic(not ideal but it was quick and dirty, and that's all I needed). Since you're looking at the topic, you might find the following interesting too: http://www.altera.com/literature/manual/stx_cookbook.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=synthesis%20cookbook Feel free to post what you're trying to do(and why), as you might get some useful feedback.
