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Honored ContributorAOC compile error
I compiled my OpenCL code with AOC 17.1.2 Build 304 and got cryptic error messages shown below. Can anyone please let me know what causes such crash?
-- aocl-llc: /build/swbuild/SJ/nightly/17.1.2/304/l64/p4/acl/llvm/include/llvm/Support/Casting.h:194: typename llvm::cast_retty<To, From>::ret_type llvm::cast(const Y&) [with X = llvm::Constant, Y = const llvm::Value*]: Assertion `isa<X>(Val) && "cast<Ty>() argument of incompatible type!"' failed. 0 libLLVM-3.0.so 0x00007f354bbfd08f 1 libLLVM-3.0.so 0x00007f354bbff002 2 libpthread.so.0 0x00007f354a82e330 3 libc.so.6 0x00007f3549846c37 gsignal + 55 4 libc.so.6 0x00007f354984a028 abort + 328 5 libc.so.6 0x00007f354983fbf6 6 libc.so.6 0x00007f354983fca2 7 libLLVM-3.0.so 0x00007f354b34fd47 grif::XNodeROMBlockInstance::XNodeROMBlockInstance(llvm::CallInst*, grif::XNodeGroup*) + 1815 8 libLLVM-3.0.so 0x00007f354b3506c5 grif::XNodeROMLookup::XNodeROMLookup(llvm::Value*, grif::XNodeGroup*) + 437 9 libLLVM-3.0.so 0x00007f354b28167f grif::XNodeFactory::TranslateLLVMCall_Instruction(llvm::Value*, grif::XNodeGroup*) + 1903 10 libLLVM-3.0.so 0x00007f354b283232 grif::XNodeFactory::TranslateLLVMInstruction(llvm::Value*, grif::XNodeGroup*) + 1650 11 libLLVM-3.0.so 0x00007f354b283464 grif::XNodeFactory::Create(llvm::Value*, grif::XNodeGroup*, acl::BasicBlockLiveIO*) + 180 12 libLLVM-3.0.so 0x00007f354b38a55a grif::XNodeStallSyncCluster::add_cluster_nodes(std::vector<llvm::Instruction*, std::allocator<llvm::Instruction*> > const&) + 1098 13 libLLVM-3.0.so 0x00007f354b0ccb2f grif::util::create_netlist_nodes(llvm::Function&, acl::BasicBlockLiveIO*, grif::XNodeGroup*) + 303 14 libLLVM-3.0.so 0x00007f354b0bb008 acl::DSDKGenerate::Generate(llvm::Function&) + 584 15 libLLVM-3.0.so 0x00007f354b0bde33 acl::DSDKGenerate::runOnFunction(llvm::Function&) + 83 16 libLLVM-3.0.so 0x00007f354b0bebc0 acl::DSDKGenerate::runOnModule(llvm::Module&) + 2768 17 libLLVM-3.0.so 0x00007f354be1eb51 llvm::MPPassManager::runOnModule(llvm::Module&) + 577 18 libLLVM-3.0.so 0x00007f354be1ecfb llvm::PassManagerImpl::run(llvm::Module&) + 187 19 aocl-llc 0x000000000040bdc0 main + 5360 20 libc.so.6 0x00007f3549831f45 __libc_start_main + 245 21 aocl-llc 0x00000000004098e9 Stack dump: 0. Program arguments: aocl-llc -march=griffin -board /IntelFPGA/17.1/hld/board/a10_ref/hardware/a10gx/board_spec.xml -dbg-info-enabled my_fpga.bc -o my_fpga.v 1. Running pass 'Generate DSDK netlist and HDL' on module 'my_fpga.bc'. Aborted (core dumped) Error: Verilog generator FAILED.2 Replies
Altera_ForumThese types of LLVM errors generally happen when the kernel is FPGA-unfriendly, or too complex for the compiler to handle. There is no fixed cause for them, nor is there a fixed solution. You can generally bypass them by refactoring your kernel and making it more FPGA-friendly. Other than that, you can also directly open a ticket with Altera and report the issue since this is basically a compiler bug, and only they can fix it.
rp519New Contributor
I am having the same issue, is there a way to debug the kernel to determine what part of it is FPGA unfriendly. I only say this, as when emulating the kernel, it builds and runs absolutely fine. However, whenever I try to compile it to the FPGA hardware (on the Intel Devcloud), I run into this error.
Compiler Warning: Limiting maximum work-group size to 512 in function infect_sweep(...) to support private memory.terminate called after throwing an instance of 'std::bad_alloc'what(): std::bad_allocStack dump:0. Program arguments: /glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/linux64/bin/../../llvm/bin/aocl-llc -march=fpga -board /opt/a10/inteldevstack/a10_gx_pac_ias_1_2_1_pv/opencl/opencl_bsp/hardware/pac_a10/board_spec.xml -pass-remarks-input=pass-remarks.yaml -dbg-info-enabled sweep_hardware.bc -o sweep_hardware.v1. Running pass 'Generate DSDK netlist and HDL' on module 'sweep_hardware.bc'./glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN4llvm3sys17RunSignalHandlersEv+0x4c)[0x7f62bbf4187c]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(+0xe209cc)[0x7f62bbf419cc]/lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f62baf14980]/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f62ba217fb7]/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f62ba219921]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../../linux64/lib/dspba/linux64/libstdc++.so.6(_ZN9__gnu_cxx27__verbose_terminate_handlerEv+0x125)[0x7f62bac11c25]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../../linux64/lib/dspba/linux64/libstdc++.so.6(+0x8fa06)[0x7f62bac0fa06]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../../linux64/lib/dspba/linux64/libstdc++.so.6(+0x8fa51)[0x7f62bac0fa51]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../../linux64/lib/dspba/linux64/libstdc++.so.6(+0x8fc93)[0x7f62bac0fc93]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../../linux64/lib/dspba/linux64/libstdc++.so.6(+0x9016c)[0x7f62bac1016c]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4e0152)[0x7f62ba06a152]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4da3c6)[0x7f62ba0643c6]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4125af)[0x7f62b9f9c5af]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4d78e4)[0x7f62ba0618e4]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4da58e)[0x7f62ba06458e]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4db4d7)[0x7f62ba0654d7]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4db81c)[0x7f62ba06581c]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4e5932)[0x7f62ba06f932]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(_ZN4dsdk14GlobalTypePass7getTypeERKNS_4WireERKSt6vectorIPKNS_5BlockESaIS7_EE+0xd9)[0x7f62ba065d2f]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x4fdd12)[0x7f62ba087d12]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(_ZN4dsdk19UnrollAggregatePass5applyERNS_16ModelPassContextE+0x329)[0x7f62ba084ea3]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(_ZN4dsdk9ModelPass5applyERNS_11PassContextE+0x65f)[0x7f62b9f73215]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(+0x3f428a)[0x7f62b9f7e28a]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(_ZN4dsdk11PassResults3runERKSt6vectorINS_8internal11PassRequestESaIS3_EERKSt3setIS3_St4lessIS3_ES4_E+0x11)[0x7f62b9f761e3]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libdsdk.so(_ZNK4dsdk13PassScheduler5applyERNS_6DesignE+0x2f)[0x7f62b9f7623d]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libgenerationlib.so(_ZN19generation_internal15runPreCModelGenERN4dsdk16CModelGenContextERNS0_6DesignE+0x10fc)[0x7f62c1438f21]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/../../linux64/lib/dspba/linux64/libgenerationlib.so(_Z18runModelGenerationRN4dsdk16CModelGenContextERNS_5ModelERKSt6vectorIPKNS_5BlockESaIS7_EE+0x734)[0x7f62c141ff44]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN4grif10XNodeGroup8scheduleERN4dsdk13ModelTreePassEbbbbbbb+0x5d7)[0x7f62be7e15f7]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN4grif18Pass_SchedModelGen7runPassEPNS_5XNodeERN4dsdk13ModelTreePassE+0x109)[0x7f62be659c49]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN3acl12DSDKGenerate8GenerateEPNS_27ChannelConnectivityAnalysis6KernelE+0x2b47)[0x7f62be5a2587]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN3acl12DSDKGenerate11runOnKernelEPNS_27ChannelConnectivityAnalysis6KernelE+0x111)[0x7f62be5a4781]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN3acl12DSDKGenerate11runOnModuleERN4llvm6ModuleE+0xe26)[0x7f62be5a57f6]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/llvm/bin/../lib/libLLVM-9svn.so(_ZN4llvm6legacy15PassManagerImpl3runERNS_6ModuleE+0x401)[0x7f62bc087561]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/linux64/bin/../../llvm/bin/aocl-llc(+0x229db)[0x55f79fb369db]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/linux64/bin/../../llvm/bin/aocl-llc(main+0x475)[0x55f79fb271a5]/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xe7)[0x7f62ba1fabf7]/glob/development-tools/versions/fpgasupportstack/a10/1.2.1/intelFPGA_pro/hld/linux64/bin/../../llvm/bin/aocl-llc(+0x13399)[0x55f79fb27399]Aborted (core dumped)
