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Altera_Forum's avatar
Altera_Forum
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14 years ago

Anyway to find output ports on a clock in tcl?

I'm delving into sdc files and tcl and was wondering if there is a way to find all the output ports clocked by a certain clock for a source synchronous design. My first guess is to make a fanou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I noticed you're assigning the clock CLK_G0X4, which is internally to the FPGA, to the output register. It's good practice to create virtual clock for these. The exception is source-synchronous outputs, whereby you want to put a generated clock on the port driving the clock out and then use that as the -clock option.

What is it you're trying to do? I've never seen a need to find what clock drives the output register and then use that external and wondering if there is another way around it.