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Altera_Forum's avatar
Altera_Forum
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11 years ago

Any difference between these processes ?

Is there any deep meaning behind the "standard" process declaration regarding "en" signal ? : process (clk, rst) begin if (rst = '0') then q1 <= '0'; elsif (rising_edge(clk)) then if ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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I don't think "en" signal from my second example is in the sensitivity list...

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It's not, and with good reason.

If you added it, it would simulate is if it was a gated clock. Without it in there, it simulates like a register with clock enable.

My point is, with the tool now able to use sensitivity lists to make different logic, it might just chose between the two options above, depending only on the sensitivity list.