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Altera_Forum's avatar
Altera_Forum
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11 years ago

Any difference between these processes ?

Is there any deep meaning behind the "standard" process declaration regarding "en" signal ? : process (clk, rst) begin if (rst = '0') then q1 <= '0'; elsif (rising_edge(clk)) then if ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Interestingly, newer quartus versions are using the sensitivity list to alter circuit generation to match the RTL more closely, so I wouldnt be surprised if it actually did gate the clock if en was put in the sensitivity list.

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I don't think "en" signal from my second example is in the sensitivity list...