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The tool is smart enough not to gate clock with enable but I don't always trust the software team which made the compilers
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Modern version yes, but older versions maybe not.
Interestingly, newer quartus versions are using the sensitivity list to alter circuit generation to match the RTL more closely, so I wouldnt be surprised if it actually did gate the clock if en was put in the sensitivity list.
As Kaz pointed out, the 2nd method is not recommended, and is not in the RTL coding guidelines written by altera, which they will always use as an excuse when something doesnt work...
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