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Altera_Forum's avatar
Altera_Forum
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11 years ago

Any difference between these processes ?

Is there any deep meaning behind the "standard" process declaration regarding "en" signal ? : process (clk, rst) begin if (rst = '0') then q1 <= '0'; elsif (rising_edge(clk)) then if ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I don't think they are different but the second one is not recommended template and is not necessary.

The tool is smart enough not to gate clock with enable but I don't always trust the software team which made the compilers

Moreover you may not put enable on all registers in the process.