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Altera_Forum
Honored Contributor
11 years agoAnother beginners question
Being new to FPGA's ( started yesterday ) when I was given an Altera DE2-115 I find I keep coming up with lots of questions that I dont know the answer to I have been reading all I can in t...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Hi Dave Thanks for the last 2 replies and the encouragement I looked at what you had changed in my code and I think its making sense to me , however I tried compiling it and it failed Part of your code said
architecture Counter of Led_Blink is
signal count : unsigned(27 downto 0);
signal q_out : std_logic(3 downto 0); **** This is the line the compiler comlains about however Quartus claims , Error (10380): VHDL error at Led_Blink.vhd(21): std_logic type is used but not declared as an array type and I dont know enough to know why its telling me this --- Quote End --- It's a typo -- the signal q_out should be declared as a std_logic_vector(3 downto 0);