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Altera_Forum
Honored Contributor
11 years agoAnother beginners question
Being new to FPGA's ( started yesterday ) when I was given an Altera DE2-115 I find I keep coming up with lots of questions that I dont know the answer to I have been reading all I can in t...
Altera_Forum
Honored Contributor
11 years agoHi Dave
Altered the faulty line to change q_out from std_logic to std_logic_vector and still compiling failed but this time I was able to sort it out myself the output of my counter " q " takes the value of your " q_out" in the line q<= q_out; but near the begining where " q " is declared in the counter entity It had it as an unsigned , I changed it now to also be a std_logic_vector and it works fine now I even added a bit more decoding to use all the counts of the 4 bits and I now get 0-9 and A-F I left the lines in ... when others => Dec_Out <= "1111111"; If I understand it correctly thats so it wont try to display something if one of the outputs were to become an undefined or high impedance type output Out of interest I know I use <= to assign the value of the item on the right to the one on the left as in the line q <= q_out but in the case statement there are a lot of => symbols , what does => signify ? like when others => Dec_Out <= "1111111"; I will look at the 3 links you gave me in the morning when I am more awake ( its been a long day) and taking of that I had told my wife that judging from your user name , you are at Caltech, She said as you have already answered my last mail you must be up quite early, Are you not about 8 hours behind us ? Don