Another beginners question

Your code is not quite right ... your counter is not 28-bits wide. You've solved a synthesis error by reducing your counter width. Here's the fixed code;

Library IEEE;
Use IEEE.numeric_std.all;
use IEEE.STD_Logic_1164.all;
entity Led_Blink is
    port
    (
    
clk    : in  STD_Logic;
q    : out unsigned (3 downto 0);
Dec_Out :out unsigned (6 downto 0)
        );
    end Led_Blink;
architecture Counter of Led_Blink is
signal count : unsigned(27 downto 0); 
signal q_out : std_logic(3 downto 0); 
begin
-- 28-bit counter
process (clk)
begin
    if rising_edge (clk) then
        count <= count + 1;
    end if ;
end process;
-- Extract the 4-MSBs and cast unsigned to std_logic_vector
q_out <= std_logic_vector(count(27 downto 24));
-- 4-bit output (pre-VHDL-2008 would not let you read 'output' ports)
q <= q_out;
-- Decode the 4-bit count
Process (q_out)
begin
    case q_out is
    when "0000" =>
    Dec_Out <= "1000000";
    when "0001" =>
    Dec_Out <= "1111001";
    when "0010" =>
    Dec_Out <= "0100100";
    when "0011" =>
    Dec_Out <= "0110000";
    when "0100" =>
    Dec_Out <= "0011001";
    when "0101" =>
    Dec_Out <= "0010010";
    when "0110" =>
    Dec_Out <= "0000011";
    when "0111" =>
    Dec_Out <= "1111000";
    when "1000" =>
    Dec_Out <= "0000000";
    when "1001" =>
    Dec_Out <= "0011000";
    when others =>
    Dec_Out <= "1111111";
    end case;
end process ;    
end Counter;

Note how I created an internal signal q_out with the 4 MSBs of the counter that was then used as the input to the 7-segment decoder logic? If I did not do that, I would have had to define the q output as buffer. That does not descibe the logic "correctly" as far as I am concerned, so I typically introduce an internal signal. I'm pretty sure VHDL-2008 allows you to read "output" ports, but I don't mind the coding style of using internal signals, so I still use them.

Cheers,

Dave