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Altera_Forum
Honored Contributor
11 years agoAnother beginners question
Being new to FPGA's ( started yesterday ) when I was given an Altera DE2-115 I find I keep coming up with lots of questions that I dont know the answer to I have been reading all I can in t...
Altera_Forum
Honored Contributor
11 years agoHi Dave
I went online to find examples so I could see what they are doing and hopefully cobble some bits together to make mine So far I had only used STD_LOGIC_1164 but looking online the example that looked most usefull used IEEE.Numeric.STD From this I think they used " Unsigned " . To be honest I dont understand why they used it but gave it a go anyway I made my entity with a clk input and q output (27 downto 0) for the architecture I declared a signal called count and told it on the rising edge of clk to assign the value of " count + 1 " to the present value of "count" then told it that "q" is assigned this new updated value of "count" It took a few goes to get the syntax right so that everything compiled ok but eventually got there I assigned the pins so that the 50Mhz clk went to the clk input and I chose several tries at which "q" I used for the output till I found that q(24) seemed a good speed I programed it to the DE2-115 and it did exactly as I wanted , flashing the first LED on and off , but for some reason there are random characters running across the LCD screen too, I dont know why as I have assigned no other pins ? Once this was working I made a second copy of the program but this time assigned the outputs Q24-Q27 to four LEDs and instead of feeding pulses from the 50Mhz clock I used one of the push buttons , so that it gave a binary count on the LEDs that increased with each push of the button It skipped now and again but I expect that is just switch bounce I have been thinking about the 7 segment display and decoding it I can see that if I take my 4 bit binary output from this last design that I could possibly work out how to decode it using case statements. If I make it have (3 downto 0) for the 4 inputs and (6 downto 0) for the 7 outputs to the segments What I am not sure of is can I make this second entity and architecture for the decoder in the same file as the counter section or can I only have one entity per VHD file in which case I am not sure how I make one file talk to the other , thats something else I must read up on anyway , this was my code that I wrote . It probably isnt elegant or efficient , but it does workLibrary IEEE;
Use IEEE.numeric_std.all;
use IEEE.STD_Logic_1164.all;
entity Led_Blink is
port
(
-- Input ports
clk : in STD_Logic;
-- Output ports
q : out unsigned (27 downto 0)
);
end Led_Blink;
architecture Counter of Led_Blink is
signal count : unsigned(27 downto 0);
begin
process (clk)
begin
if rising_edge (clk) then
count <= count + 1;
end if ;
end process ;
q<= (count);
end Counter;
Cheers Don --- Quote Start --- Create a counter and use the MSB of the counter to drive the LED. The width of the counter is as many bits as is needed to blink at the rate you desire, eg., clock frequency x 0.5s for a half-second blink period. Then when you get to the 7-segment display, you send the 4 MSBs of that counter (or one that is slightly wider) to a 4-input to 7-segment output decoder. Take a shot at it, and then I'll show you some examples that use generics and floating-point math to calculate the bit-widths (the pre-processor does the math, rather than synthesizing it into hardware). Cheers, Dave --- Quote End ---