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Altera_Forum
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18 years ago

An issue with signal tapping using SignalTapII analyser

Hi, I want to tap and analyse the bits coming out of ADC to the FPGA in my board. I have declared all the bits as a signal in the code. But in the nodelist of SignalTapII pre-sy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Do the signals go anywhere once inside the chip. Any signal that doesn't eventually feed an output will be trimmed away by the optimizer and disappears. If necessary, just tie all the lines to a multi-input AND gate and feed this to a single dummy output.