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Altera_Forum
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18 years ago

An issue with signal tapping using SignalTapII analyser

Hi, I want to tap and analyse the bits coming out of ADC to the FPGA in my board. I have declared all the bits as a signal in the code. But in the nodelist of SignalTapII pre-sy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks for ur consideration. I have tried all that u suggested, but still I cannot find the

name of the signal in place aforesaid.

But I have one doubt regarding memory issue. Can the allocation of memory, for declaration of these values as a signals, create the problem?