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Altera_Forum's avatar
Altera_Forum
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18 years ago

An issue with signal tapping using SignalTapII analyser

Hi, I want to tap and analyse the bits coming out of ADC to the FPGA in my board. I have declared all the bits as a signal in the code. But in the nodelist of SignalTapII pre-sy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Try using the "SignalTap II: post-fitting" Node Finder filter.

Quartus might have created names that are similar to but slightly different from what you have in your source file. Usually the difference is at the end of the name. Try putting a wildcard at the end of the node name in the Node Finder.