An important warning confused me--tri-state nodes do not directly drive top-level

Hi all,

Recently I compile a project in Quartus 9.0 and make some changes.

The results comes out with some strange warnings:

Tri-state nodes do not directly drive top-level.

I look up in the project

{

entity bidir is

port(

clk : in std_logic;

enable:in std_logic;

data: inout std_logic_vector(7 downto 0)

);

end bidir;

architecture behavior of bidir is

component test

port(

datain :in std_logic_vector(7 downto 0);

clk : in std_logic;

enable :in std_logic;

dataout:in std_logic_vector(7 downto 0)

)

end component;

signal data_reg : in std_logic_vector(7 downto 0);

begin

u1: test

port map(

datain => data,

clk => clk,

enable => enable,

dataout =>data_reg --data_reg is tri-state register

);

data <= data_reg when (enable = '1') else (others = 'Z');

end behavior;

}

I simulate the code in the ModelSim platform and the result doesn't give such warning.

I'm not sure whether the warning will affect the real hardware function.

Could anyone give me some advice?(It's better not to change the codes)

Best Regards.