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In the present design, there's no real purpose for tri-stating dataout of test, because it's the exclusive driver of the connected net in the design hierarchy.
Basically there are two purposes of tristatable signals in lower design entities;
- driving an external tristate pin. No warning will be issued
- driving an internal "virtual" tristate signal. This can be reasonable to implement bus-like bidirectional interconnecting signals, but has to be translated to muxes by the compiler, as said. Will usually give some warnings.
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Thank you for help.
The 'test' model is a common module used many times in my project.
The 'dataout' port should be set as 'Z' when the enable signal is '0'. or it will get errors.
such as list
u1: test
port map(
sel => enable1,
dataout =>data_reg,
....
);
data <= data_reg when (ebable1 = '1') else (others => 'Z');
u2:test
port map(
sel => enable2,
dataout =>data_reg,
....
);
data <= data_reg when (ebable2 = '1') else (others => 'Z');
....
if I set dataout as '0' when 'sel' is '0' or keep the value as same as before.The compiler will give errors: can't be assigned more than one value.
Best Regards.
Honored Contributor
