An important warning confused me--tri-state nodes do not directly drive top-level

Declaring a signal type inconsistently in a component prototype and the actual entity code can result in strange unspecfic compilation errors and should be strictly avoided. (in versus out for dataout in the original code)

In the present design, there's no real purpose for tri-stating dataout of test, because it's the exclusive driver of the connected net in the design hierarchy.

Basically there are two purposes of tristatable signals in lower design entities;

- driving an external tristate pin. No warning will be issued

- driving an internal "virtual" tristate signal. This can be reasonable to implement bus-like bidirectional interconnecting signals, but has to be translated to muxes by the compiler, as said. Will usually give some warnings.

If you are interested to know how your behavioral code is implemented, look at the RTL and gate level netlist schematic view in Quartus.