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Altera_Forum
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11 years ago

Am I use the VERILOG FUNCTION correctly?

Hi:):),

I'll be grateful and appreciate if somebody can help me to solve my problem.

I'm a dummy in verilog and FPGA. Currently, I'm using Altera Cyclone IV to develop a IO card with PCI bus interface. I develop my code using state machine. The 32-bits data sent from the PC is being decoded based on the PCI byte enable signal before further processing in firmware.

I'm using verilog function for decoding the data received from PC [function name: receiveDataFromPCI(benReg,l_dato)].

There will be another following post to show some part of my code of one of the state machine.

1) First Trial: using verilog function call.

In first trial, I found out that dataReg register fail to give me the correct value even though benReg and l_dato signals are correct.

Then, I changed to another way to write my code without using the verilog function:-

2) Second Trial: without using verilog function call.

For the second trial, dataReg register changes its value based on benReg and l_dato signals as expected.

Two version of the source file are attached in this thread.

Here, are my doubts that really need to be advised:

1. I have mixed using blocking and non-blocking assignment in my first trial code. Blocking assignment is used in a function whereas non-blocking assignment is used in process block (always block). Am I using the verilog function correctly?

2. Although second trial code can function properly, any suggestion on how if I want to reuse the code? My code will become messy and not well-organised if I just simply copy and paste that portion of code in any where that I want to decode the data received via PCI bus.

3. Is it a good practice to using verilog function or task?

I'm really look forward and appreciate somebody can provide his/her precious suggestion and advices.

Thank you very much!:-P

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    There will be another following post to show some part of my code of one of the state machine.

    --- Quote End ---

    1) First Trial: using verilog function call

    pIOWRITE_IN_PRGS1_BAR0:

    begin

    lt_rdyn_bar0 <=0;

    dataReg <=receiveDataFromPCI(benReg,l_dato);

    end

    /*---------------------------------------------------------------------------------------- */

    /* function name: receiveDataFromPCI */

    /* parameter : [3:0] benReg-> PCI Byte Enable Signal */

    /* [31:0] data -> Data to be return to PCI bus */

    /* return value : 32 bits data arranged corresponding to BEN signal */

    /*-----------------------------------------------------------------------------------------*/

    function [31:0] receiveDataFromPCI;

    input [3:0] benReg;

    input [31:0] data;

    begin

    if(benReg == 4'h0) //Arrangment of data in data byte path corresponding to BEN for 32bits family I/O card

    receiveDataFromPCI[31:0] =data[31:0];

    else if(benReg == 4'h1)

    receiveDataFromPCI[31:0] ={8'h00,6'h00,data[25:8]}; //Arrangment of data in data byte path corresponding to BEN for 18bits family I/O card

    else if(benReg == 4'h2)

    receiveDataFromPCI[31:0] ={8'h00,6'h00,data[25:16],data[7:0]};

    else if(benReg == 4'h4)

    receiveDataFromPCI[31:0] ={8'h00,6'h00,data[25:24],data[15:0]};

    else if(benReg == 4'h8)

    receiveDataFromPCI[31:0] ={8'h00,6'h00,data[17:0]};

    else if(benReg == 4'h3)

    receiveDataFromPCI[31:0] ={16'h0000,data[31:16]}; //Arrangment of data in data byte path corresponding to BEN for 16bits family I/O card

    else if(benReg == 4'h5)

    receiveDataFromPCI[31:0] ={16'h0000,data[31:24],data[15:8]};

    else if(benReg == 4'h6)

    receiveDataFromPCI[31:0] ={16'h0000,data[31:24],data[7:0]};

    else if(benReg == 4'h9)

    receiveDataFromPCI[31:0] ={16'h0000,data[23:8]};

    else if(benReg == 4'hA)

    receiveDataFromPCI[31:0] ={16'h0000,data[23:16],data[7:0]};

    else if(benReg == 4'hC)

    receiveDataFromPCI[31:0] ={16'h0000,data[15:0]};

    else if(benReg == 4'h7) //Arrangment of data in data byte path corresponding to BEN for 8bits family I/O card

    receiveDataFromPCI[31:0] ={24'h00_0000,data[31:24]};

    else if(benReg == 4'hB )

    receiveDataFromPCI[31:0] ={24'h00_0000,data[23:16]};

    else if(benReg == 4'hD)

    receiveDataFromPCI[31:0] ={24'h00_0000,data[15:8]};

    else if(benReg == 4'hE)

    receiveDataFromPCI[31:0] ={24'h00_0000,data[7:0]};

    else

    receiveDataFromPCI[31:0] =32'h0000_0000;[/INDENT]

    end

    endfunction

    2) Second Trial: without using verilog function call

    pIOWRITE_IN_PRGS1_BAR0:

    begin

    lt_rdyn_bar0 <=0;

    //dataReg <=receiveDataFromPCI(benReg,l_dato);

    if(benReg == 4'h0) //Arrangment of data in data byte path corresponding to BEN for 32bits family I/O card

    dataReg[PCIDATAWIDTH-1:0] <=l_dato[PCIDATAWIDTH-1:0];

    else if(benReg == 4'h1)

    dataReg[PCIDATAWIDTH-1:0] <={8'h00,6'h00,l_dato[25:8]};//Arrangment of data in data byte path corresponding to BEN for 18bits family I/O card

    else if(benReg == 4'h2)

    dataReg[PCIDATAWIDTH-1:0] <={8'h00,6'h00,l_dato[25:16],l_dato[7:0]};

    else if(benReg == 4'h4)

    dataReg[PCIDATAWIDTH-1:0] <={8'h00,6'h00,l_dato[25:24],l_dato[15:0]};

    else if(benReg == 4'h8)

    dataReg[PCIDATAWIDTH-1:0] <={8'h00,6'h00,l_dato[17:0]};

    else if(benReg == 4'h3)

    dataReg[PCIDATAWIDTH-1:0] <={16'h0000,l_dato[31:16]}; //Arrangment of data in data byte path corresponding to BEN for 16bits family I/O card

    else if(benReg == 4'h5)

    dataReg[PCIDATAWIDTH-1:0] <={16'h0000,l_dato[31:24],l_dato[15:8]};

    else if(benReg == 4'h6)

    dataReg[PCIDATAWIDTH-1:0] <={16'h0000,l_dato[31:24],l_dato[7:0]};

    else if(benReg == 4'h9)

    dataReg[PCIDATAWIDTH-1:0] <={16'h0000,l_dato[23:8]};

    else if(benReg == 4'hA)

    dataReg[PCIDATAWIDTH-1:0] <={16'h0000,l_dato[23:16],l_dato[7:0]};

    else if(benReg == 4'hC)

    dataReg[PCIDATAWIDTH-1:0] <={16'h0000,l_dato[15:0]};

    else if(benReg == 4'h7) //Arrangment of data in data byte path corresponding to BEN for 8bits family I/O card

    dataReg[PCIDATAWIDTH-1:0] <={24'h00_0000,l_dato[31:24]};

    else if(benReg == 4'hB )

    dataReg[PCIDATAWIDTH-1:0] <={24'h00_0000,l_dato[23:16]};

    else if(benReg == 4'hD)

    dataReg[PCIDATAWIDTH-1:0] <={24'h00_0000,l_dato[15:8]};

    else if(benReg == 4'hE)

    dataReg[PCIDATAWIDTH-1:0] <={24'h00_0000,l_dato[7:0]};

    else

    dataReg[PCIDATAWIDTH-1:0] <=32'h0000_0000;[/INDENT]

    end