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Honored Contributor

12 years ago

Always block within always block

Hi guys, Is it possible to use always@block within always block? The reason I want to do that is I try to construct multiple synchronised blocks using For loop, and you need to put loop stateme...

Altera_Forum

Honored Contributor

12 years ago

You'll want a generate statement

In this example: http://www.asic-world.com/verilog/verilog2k2.html

You can replace memory U with your always structure

Just be sure you don't generate multiple drivers for whatever reg you are writing

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Always block within always block

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