altlvds Transmitter in MegaWizard

Hi All,

I am currently using 'altlvds' for transmitting data(See Below).

For tx_in I have assigned a 10 bit data and for tx_inclock I assigned 100Mhz CoreClock.

I am not getting any data from the output ports.

Could anyone please help me in regard?

Thanks in advance

Regards

Sandeep

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY LvdsTx IS

PORT

(

tx_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

tx_inclock : IN STD_LOGIC := '0';

tx_coreclock : OUT STD_LOGIC ;

tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

tx_outclock : OUT STD_LOGIC

);

END LvdsTx;

ARCHITECTURE SYN OF lvdstx IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC ;

SIGNAL sub_wire2 : STD_LOGIC ;

COMPONENT altlvds_tx

GENERIC (

common_rx_tx_pll : STRING;

deserialization_factor : NATURAL;

implement_in_les : STRING;

inclock_data_alignment : STRING;

inclock_period : NATURAL;

inclock_phase_shift : NATURAL;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

number_of_channels : NATURAL;

outclock_alignment : STRING;

outclock_divide_by : NATURAL;

outclock_phase_shift : NATURAL;

outclock_resource : STRING;

output_data_rate : NATURAL;

registered_input : STRING

);

PORT (

tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

tx_outclock : OUT STD_LOGIC ;

tx_coreclock : OUT STD_LOGIC ;

tx_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

tx_inclock : IN STD_LOGIC

);

END COMPONENT;

BEGIN

tx_out <= sub_wire0(0 DOWNTO 0);

tx_outclock <= sub_wire1;

tx_coreclock <= sub_wire2;

altlvds_tx_component : altlvds_tx

GENERIC MAP (

common_rx_tx_pll => "ON",

deserialization_factor => 10,

implement_in_les => "OFF",

inclock_data_alignment => "UNUSED",

inclock_period => 10000,

inclock_phase_shift => 0,

intended_device_family => "Stratix",

lpm_hint => "CBX_MODULE_PREFIX=LvdsTx",

lpm_type => "altlvds_tx",

number_of_channels => 1,

outclock_alignment => "UNUSED",

outclock_divide_by => 10,

outclock_phase_shift => 0,

outclock_resource => "AUTO",

output_data_rate => 1000,

registered_input => "TX_CORECLK"

)

PORT MAP (

tx_in => tx_in,

tx_inclock => tx_inclock,

tx_out => sub_wire0,

tx_outclock => sub_wire1,

tx_coreclock => sub_wire2

);

END SYN;