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Altera_Forum
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9 years ago

altlvds_rx ModelSim simulation missing data

I have a simulation that consists of an altlvds_rx block with an external PLL. Every block in the system looks to be functioning correctly, except the altlvds_rx block which looks to have all the cor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

After considerable struggles with PLL simulations, I've decided to just write code in my test bench to generate the desired clock signals. It's much easier than working with problematic simulations.