Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI've had problems using the altlvds_rx with external PLL in simulation as well. There is an issue with the simulated PLL that causes one of the internal counters (I forget which one, maybe C) to be out by 1 count which means that the clocks are out of phase. It took me a long time to figure out that it was the simulation model causing the problems rather than the calculations in the ALTLVDS datasheet.
I never found a satisfactory work around. To get it to work I ended up having to adjust the phase of one of the clocks in the simulation. The trouble is it's been two years since I did the simulation, so can't remember how I made it work. I'll try to see if I have any old testbenches from a couple of years with the changes in.