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Altera_Forum's avatar
Altera_Forum
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11 years ago

Altera Qsys Generated Pci Express Wrapping

I have problem with pci express avalon busses. Altera's ip core has may input output on generated module. I didnt figure out how to drive all those io.

My board has following pci express signals,

PCIE_PERST_N PCIE_REFCLK_P PCIE_RX_P PCIE_TX_P PCIE_WAKE_N

And i only need tx_en, tx_data, tx_busy, rx_en,rx_data.

How can i wrap qsys generated module?

Thanks.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You will need those signals to drive the PCIe HIP (module). For example the refclk is the PCIe reference clock that the transceivers need, the perstn is a reset input that is also derived from an input pin. There is quite a reasonable Altera pdf explaining the PCIe Avalon MM core, so it's best to have a read first, or you will not understand how to drive the core.