Forum Discussion
New Contributoraltera_pll Fractional-N PLL error using physical output clock parameters
The Fvco achieved by the settings that you had made is beyond the limit specified in the datasheet. For Arria V, Stratix V and Cyclone V device the Fvco min = 600 MHz.
Best way is to first enter the 'Desired Frequency' and let the tool calculate the parameters. You may then adjust the values if more refinement is required.
Please refer, Altera PLL IP Core User Guide, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf and AN 661, https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html for more details.
Regards.
Regular ContributorThe Fvco achieved by the settings that you had made is beyond the limit specified in the datasheet. For Arria V, Stratix V and Cyclone V device the Fvco min = 600 MHz.
Best way is to first enter the 'Desired Frequency' and let the tool calculate the parameters. You may then adjust the values if more refinement is required.
Please refer, Altera PLL IP Core User Guide, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf and AN 661, https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html for more details.
Regards.
HypeInstThank you for your response! I'm sorry that I previously missed the Fvco limitations. I see those in the datasheet now and will revise accordingly. Thanks again!
