New ContributorALT_SLD_FAB Errors
Hello,
I tried to implement Partially Reconfiguring Design
flow to my project, according to https://www.intel.com/content/www/us/en/programmable/documentation/ihj1482170009390.html after Step 7: Compiling the Base Revision, I get bunch of errors that has no explanation,
Info(11171): Finished IP generation for the debug fabric: alt_sld_fab_0.
Info(16821): Verilog HDL info at alt_sld_fab_0_alt_sld_fab_191_22dgnwq.v(144): going to vhdl side to elaborate module alt_sld_fab_0_altera_sld_jtag_hub_191_jqbwo4y
Info(19337): VHDL info at alt_sld_fab_0_altera_sld_jtag_hub_191_jqbwo4y.vhd(13): executing entity "alt_sld_fab_0_altera_sld_jtag_hub_191_jqbwo4y(device_family="Arria 10",count=1,n_sel_bits=1,n_node_ir_bits=4,node_info="00010011100010000110111000000000",compilation_mode=0,broadcast_feature=0,force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=2)(1,8)(1,0)(1,32)" with architecture "rtl"
Info(19337): VHDL info at sld_jtag_hub.vhd(89): executing entity "sld_jtag_hub(device_family="Arria 10",n_nodes=1,n_sel_bits=1,n_node_ir_bits=4,node_info="00010011100010000110111000000000",broadcast_feature=0,force_pre_1_4_feature=0,negedge_tdo_latch=0,bridge_start_index=2)(1,8)(31,0)" with architecture "rtl"
Info(19337): VHDL info at sld_hub.vhd(1554): executing entity "sld_shadow_jsm(ip_major_version=1,ip_minor_version=5)" with architecture "rtl"
Info(19337): VHDL info at sld_rom_sr.vhd(5): executing entity "sld_rom_sr(n_bits=64)" with architecture "INFO_REG"
Info(16822): Verilog HDL info at alt_sld_fab_0_alt_sld_fab_191_22dgnwq.v(144): back to verilog to continue elaboration
Info(11170): Starting IP generation for the debug fabric: alt_sld_fab_1.
Warning(11175): Alt_sld_fab_1.alt_sld_fab_1.alt_sld_fab_1: SLD fabric agents are not connected as there are no hosts
Error(11176): Alt_sld_fab_1.alt_sld_fab_1: add_instance: Can't create component type altera_sld_agent_endpoint_tieoff
Info(11172): invoked from within
Info(11172): "add_instance sldfabric_t0 altera_sld_agent_endpoint_tieoff"
Info(11172): ("eval" body line 7)
Info(11172): invoked from within
Info(11172): "eval $tcl"
Info(11172): (procedure "compose" line 36)
Info(11172): invoked from within
Info(11172): "compose"
Info(11172): invoked from within
Info(11172): "interp eval $slave {
Info(11172): Compose
Info(11172): }"
Warning(11175): Alt_sld_fab_1.alt_sld_fab_1.alt_sld_fab_1.splitter.nodes: Interface has no signals
Error(11176): Alt_sld_fab_1.alt_sld_fab_1.alt_sld_fab_1.ocpfabric.clock: ocpfabric.clock must be connected to a clock output
Info(11172): ***************************************************************
Info(11172): Quartus is a registered trademark of Intel Corporation in the
Info(11172): US and other countries. Portions of the Quartus Prime software
Info(11172): Code, and other portions of the code included in this download
Info(11172): Or on this DVD, are licensed to Intel Corporation and are the
Info(11172): Copyrighted property of third parties. For license details,
Info(11172): Refer to the End User License Agreement at
Info(11172): Http://fpgasoftware.intel.com/eula.
Info(11172): ***************************************************************
Error(11176): Error opening /home/dovydas/Desktop/LTU_Rocket_Soc_up_190903/qdb/_compiler/LTU_SoC/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_1/alt_sld_fab_1.ip.
Info(11172): ***************************************************************
Info(11172): Quartus is a registered trademark of Intel Corporation in the
Info(11172): US and other countries. Portions of the Quartus Prime software
Info(11172): Code, and other portions of the code included in this download
Info(11172): Or on this DVD, are licensed to Intel Corporation and are the
Info(11172): Copyrighted property of third parties. For license details,
Info(11172): Refer to the End User License Agreement at
Info(11172): Http://fpgasoftware.intel.com/eula.
Info(11172): ***************************************************************
Info(11171): Finished IP generation for the debug fabric: alt_sld_fab_1.
Error(19882): Automatic debug logic insertion has failed.
Error: Flow failed:
Info(144001): Generated suppressed messages file /home/dovydas/Desktop/LTU_Rocket_Soc_up_190903/output_files/LTU_SoC.syn.smsg
Error: Quartus Prime Synthesis was unsuccessful. 5 errors, 109 warnings
Error: Peak virtual memory: 2078 megabytes
Error: Processing ended: Thu Dec 5 16:03:10 2019
Error: Elapsed time: 00:00:35
Error(293001): Quartus Prime Full Compilation was unsuccessful. 6 errors, 109 warnings
This is the first time I encountered such errors. I did some internet research, however, was not able to find any solution to this problem. If anyone who has encountered this and was able to solve the problem successfully could guide me through this problem, I would greatly appreciate it.
