New ContributorAgilex gated clock conversion
Hello,
I'm running Quartus 21.3 building for an Agilex FPGA. The clock gate conversion isn't working even though I have this set in the project file:
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
in the *.syn.rpt I see this message:
Warning (20807): Automatic Gated Clock Conversion is enabled, but no clocks are explicitly identified and this family does not support automatic clock recognition during synthesis. Add GATED_CLOCK_CONVERSION_BASE_CLOCK assignments to properly identify base clocks.
The SDC constraints don't seem to make a difference on the clock roots that I want converted. Furthermore, I haven't found a way for the tool to take the GATED_CLOCK_CONVERSION_BASE_CLOCK assignment.
Any assistance would be appreciated.
Hi,
[First Post Edited]
Had to use both:
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK ON
Then Following design synthesis, view the results of gated clock conversion in the Gated Clock Conversion Details report (.syn.rpt under Gated Clock Conversion Details). The report lists all converted and unconverted gated clocks with their base clocks. For unconverted gated clocks, the report specifies the reason the clock is not converted.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
