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IanD's avatar
IanD
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Agilex gated clock conversion

Hello, I'm running Quartus 21.3 building for an Agilex FPGA. The clock gate conversion isn't working even though I have this set in the project file: set_global_assignment -name SYNTH_GATED_CLOCK_C...
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    [First Post Edited]

    Had to use both:

    set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON

    set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK ON

    Then Following design synthesis, view the results of gated clock conversion in the Gated Clock Conversion Details report (.syn.rpt under Gated Clock Conversion Details). The report lists all converted and unconverted gated clocks with their base clocks. For unconverted gated clocks, the report specifies the reason the clock is not converted.


    Thanks,

    Best Regards,

    Sheng


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Use this set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK ON

Then Following design synthesis, view the results of gated clock conversion in the Gated Clock Conversion Details report (.syn.rpt under Gated Clock Conversion Details). The report lists all converted and unconverted gated clocks with their base clocks. For unconverted gated clocks, the report specifies the reason the clock is not converted.


Thanks,

Best Regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.