Address comparator

"always @(posedge clock or write_addr_0 or write_addr_1 or write_addr_2 or write_addr_3)"

This is weird.

It's describing purely combinatory logic, as all the primary outputs are listed in the sensitivity list. So "posedge clk" is actually redundant.

If you want sequential logic instead, leave just the "posedge clk".

That said, your comparisson logic looks broken. I really don't see why you bitwese comparison logic will produce 8'b0000_0001 when you have address collisions.

Maybe it produces 8'b1111_1111 ?

But I suggest you use something simpler and let the synthesis tool sort it out.

wire_01 = write_addr_0 != wire_addr1; // Produces a single bit result!

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