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To avoid confusion I would declare the presumed unsigned value as signed "0"&value.
Though we can use resize for either signed or unsigned but I am not sure what happens if we resize an unsigned value cast as signed inside this function. I would rather just avoid it.
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I agree with Kaz. Since your operation involves both '+' and '-' operators, it makes more sense to use signed numbers for the representation.
Assuming that 'relation' is an unsigned value, and given that it always has a lower bit-width than the 32-bit result, both of the following should yield identical results;
subDecRot <= STD_LOGIC_VECTOR(SIGNED(buffRot)-resize(UNSIGNED(RELATION),32));
subIncRot <= STD_LOGIC_VECTOR(SIGNED(buffRot)+resize(UNSIGNED(RELATION),32));
although the subtraction may force the conversion to signed, in which case it might be preferred to simply convert relation to unsigned without resize, i.e., just unsigned(relation).
The least ambiguous form is to use signed ...
subDecRot <= STD_LOGIC_VECTOR(SIGNED(buffRot)-resize(SIGNED('0' & RELATION),32));
subIncRot <= STD_LOGIC_VECTOR(SIGNED(buffRot)+resize(SIGNED('0' & RELATION),32));
Ultimately your code would be less confusing if the entity ports used signed and unsigned types. Those ports can then be converted to std_logic_vector when used in the higher level design.
Cheers,
Dave
Honored Contributor
