Addition problem in Quartus

Look again at the link you posted, the function is over-loaded for both SIGNED and UNSIGNED.

-- Id: R.1
  function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
  -- Result: Resizes the SIGNED vector ARG to the specified size.
  --         To create a larger vector, the new  bit positions
  --         are filled with the sign bit (ARG'LEFT). When truncating,
  --         the sign bit is retained along with the rightmost part.
  -- Id: R.2
  function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
  -- Result: Resizes the SIGNED vector ARG to the specified size.
  --         To create a larger vector, the new  bit positions
  --         are filled with '0'. When truncating, the leftmost bits
  --         are dropped.

as I comment above, the MSBs of an unsigned number are '0' extended.

--- Quote Start ---

So, if I opt for UNSIGNED (again) I have all the bits, while if I opt for SIGNED, it will have 1 bit less

--- Quote End ---

I'm not sure what you mean by this. If you need 32-bits to represent a modulo-32 bit operation, then it does not matter if that 32-bit number uses signed or unsigned representation. In either case, you still need 32-bits. I'm not sure why you think signed would need 1-bit less.

As for your RTL view ... personally I'd recommend starting with Modelsim and making sure your testbench produces the correct results, and then worry about synthesis.

Cheers,

Dave