Addition problem in Quartus

[SOLVED] [?]

Since the Integer type doesnt work at 32 bit (it uses the bit 31 as carry, as the RTL shows) I worked 2 strategies to solve it:

For the ROT counter, I shifted all the logic one bit to the right, so i actually use 31 bits

ROT  <=  buffRot(30 downto 15);
subDecRot <= STD_LOGIC_VECTOR(TO_UNSIGNED(TO_INTEGER(UNSIGNED(buffRot)) - TO_INTEGER(UNSIGNED(RELATION)),32));
subIncRot <= STD_LOGIC_VECTOR(TO_UNSIGNED(TO_INTEGER(UNSIGNED(buffRot)) + TO_INTEGER(UNSIGNED(RELATION)),32));	

For the 46 bits variables, I have implemented the sum as another VHDL file (even knowing it could be done with an function)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ADDER_46 is Port ( 
	A    : IN  STD_LOGIC_VECTOR (45 downto 0);
	B    : IN  STD_LOGIC_VECTOR (45 downto 0);
	C    : OUT STD_LOGIC_VECTOR (45 downto 0);
	COUT : OUT STD_LOGIC;
	CIN  : IN  STD_LOGIC
);
end ADDER_46;
architecture Behavioral of ADDER_46 is
signal Carry: STD_LOGIC_VECTOR (46 downto 0); 
begin
Carry(0) <= CIN;
COUT <= Carry(46);
Carry(46 downto 1) <= (A and B)or(Carry(45 downto 0) and (A or B));
C <= (A xor B)xor Carry(45 downto 0);
end Behavioral;

Still, I think the designers of Quartus should give a look at the image I have posted in the first post.